The present invention relates to a no-hit switching apparatus and, more particularly, to a no-hit switching apparatus for receiving two main signals, switching them without any hit, and selecting one of them.
In general, a no-hit switching apparatus for switching between received signals without any hit in a digital communication system stores two main signals in corresponding memory circuits in accordance with the operations of corresponding frame pulses. This apparatus realizes no-hit phase matching and switching of the two main signals by reading data from these memory circuits in accordance with a common read counter.
FIG. 4 shows a conventional no-hit switching device disclosed in Japanese Patent Laid-Open No. 6-61984. In FIG. 4, multi-frame pulse detecting circuits 21 and 22 detect the heads of multi-frames of main signals A and B to output multi-frame pulses A115 and B117. Using the multi-frame pulses A115 and B117 as triggers, write counters 31 and 32 generate write addresses for writing main signals A111 and B112 in memory circuits 11 and 12. A delay signal selecting circuit 4 compares the multi-frame pulse A115 with the multi-frame pulse B117 to output a multi-frame pulse whose absolute delay amount is larger, as a multi-frame pulse D118.
A multi-frame pulse generating circuit 5 generates a minimum-delay reading multi-frame pulse 119 for the multi-frame pulse D118 in response to a frame pulse 115. Using the reading multi-frame pulse 119 as a trigger, a read counter 6 generates a read address for reading out the main signals A and B from the memory circuits 11 and 12.
By the read address, the absolute delay amount of the signal read out from the memory circuit 11, and that of the main signal read out from the memory circuit 12 are made to match each other with the minimum delay. By controlling a selecting circuit 7 with a switching signal 114, switching of an output signal 113 can be executed without any error to the main signals A and B.
As another conventional technique of this type, Japanese Patent Laid-Open No. 3-93331 discloses the technique of detecting a phase difference between input signals in a frame phase comparator section and matching the phase of second or subsequent data to that of first data in accordance with this phase difference. Japanese Patent Laid-Open No. 1-180148 discloses the synchronization switching circuit capable of increasing the error detection rate by prolonging the error count time as much as possible.
In these conventional no-hit switching apparatuses, however, the cost is undesirably high because a memory circuit must be arranged for each main signal.
As a technique associated with the no-hit switching apparatus, Japanese Patent Laid-Open No. 8-111675 discloses the technique of generating a timing matched with the input timing of external data by a delay line and reading the external data stored in an elastic store circuit at this timing. Japanese Patent Laid-Open No. 5-122199 discloses the technique of receiving 0- and 1-system transmission signals from an existing device to detect a phase difference between them, and giving this phase difference to own 0- and 1-system transmission signals.
U.S Pat. Nos. 5,189,670 and 5,218,602 also disclose the techniques associated with the no-hit switching apparatus.
However, these associated techniques do not disclose any detailed memory circuit for storing each main signal. Therefore, in these associated techniques, no technique of decreasing the number of memory circuits for storing main signals to one is disclosed.